In a high-speed logic circuit in which signal rise and fall times are short, there are instances where it becomes necessary to treat a signal line as a transmission line of a distributed-constant circuit. For example, reflection must be taken into account when the propagation delay time of a transmission line is large in comparison with the rise and fall times of the output signal. That is, when a circuit having impedance different from the characteristic impedance of a transmission line is connected to the transmission line, reflection is produced at the point of connection. As is well known, a reflection coefficient ρ1 at the receiving end is given by the following equation:ρ1=(ZL−Z0)/(ZL+Z0)where Zs represents the output impedance of a signal source. Accordingly, if the transmission line whose characteristic impedance is Z0 is terminated at ZL=Z0 or Zs=Z0, reflection can be avoided.
FIG. 9 is a diagram schematically illustrating an input/output interface in a semiconductor integrated circuit. This shows the structure of a conventional input/output circuit so adapted that terminating resistors are connected to a signal line when the mode is the input mode. As shown in FIG. 9, this circuit includes a first input/output circuit 1100, a second input/output circuit 1200, which is connected to the first input/output circuit 1100 by wiring, for sending and receiving signals, and a reference voltage source 1300.
The first input/output circuit 1100 has an input circuit (input buffer) 1110 and an output circuit (output buffer) 1120 whose input and output ends, respectively, are connected to an input/output terminal (I/O pin) DQ that sends and receives signals bi-directionally to and from an external circuit (the circuit 1200 in FIG. 9). The first input/output circuit 1100 includes, as a termination, a control circuit 1140, terminating resistors R101 and R102 each having one end connected to the input/output pin DQ, and switches SW1 and SW2 connected between the other ends of the resistors R101 and R102 and a high-potential power supply VDDQ and low-potential power supply GND, respectively.
Assume that the first input/output circuit 1100 has been placed in the output mode (transmit mode) and that the output buffer 1120 is in the output-enable state. The output buffer 1120 includes a control circuit 1130 the inputs to which are a control signal that controls input/output and data that arrives from a data source 1150, and a CMOS inverter. The CMOS inverter comprises a P-channel MOS transistor MP101 and an N-channel MOS transistor MN101 having gates connected in common with the output of the control circuit 1130, drains tied together and connected to the input/output pin DQ, and sources connected to the high-potential power supply VDDQ and low-potential power supply GND, respectively. The data source 1150 represents an internal circuit (not shown) that supplies the control circuit 1130 of the first input/output circuit 1100 with data that is to be output from the input/output pin DQ.
The input buffer 1110 has first and second input terminals supplied respectively with an input signal from the input/output pin DQ and a reference voltage Vref from the reference voltage source 1300. The input buffer 1110 differentially amplifies a voltage between the input signal and the reference voltage Vref by an input differential pair (not shown) and outputs, to the internal circuit (not shown), a signal having a logic value that corresponds to the magnitude relationship between the input signal and reference voltage Vref. It should be noted that an arrangement might be adopted in which the input buffer 1110 are set to the OFF state when the operating mode is the output mode.
The second input/output circuit 1200 has an input circuit (input buffer) 1210 and an output circuit (output buffer) 1220 whose input and output ends, respectively, are connected to an input/output pin DQ). The second input/output circuit 1200 includes, as a termination, a control circuit 1240, terminating resistors R201 and R202 each having one end connected to the input/output pin DQ, and switches SW3 and SW4 connected between the other ends of the resistors R201 and R202 and the high-potential power supply VDDQ and low-potential power supply GND, respectively.
The output buffer 1220 has a structure similar to that of the output buffer 1120. In the example of the circuit connection shown in FIG. 9, however, the second input/output circuit 1200 is in the input mode (receive mode) and therefore the output thereof has been set in a state of high impedance. More specifically, the output buffer 1220 includes a control circuit 1230 and a CMOS inverter. The latter comprises a P-channel MOS transistor MP201 and an N-channel MOS transistor MN201 having gates connected in common with the output of the control circuit 1230, drains tied together and connected to the input/output pin DQ, and sources connected to the high-potential power supply VDDQ and low-potential power supply GND, respectively. The gate of the MOS transistor MP201 is connected to the high-potential power supply VDDQ, and the gate of the MOS transistor MN201 is connected to the low-potential power supply GND. Both of these transistors are in the OFF state.
The input buffer 1210 has first and second input terminals supplied respectively with an input signal from the input/output pin DQ and the reference voltage Vref from the reference voltage source 1300. The input buffer 1210 differentially amplifies a voltage between the input signal and the reference voltage Vref by an input differential pair (not shown) and outputs, to an internal circuit (not shown), a signal having a logic value that corresponds to the size relationship between the input signal and reference voltage Vref. It should be noted that the high potential power supply VDDQ of the input/output circuits is a power supply voltage for driving the pin DQ to the high level. Furthermore, it is not necessarily required that the internal circuit of the semiconductor integrated circuit be driven by the power supply VDDQ, and there are cases where use is made of another power supply, e.g., an internal power supply voltage obtained by stepping down VDDQ to a lower voltage.
As mentioned above, FIG. 9 illustrates an arrangement for a case where the first input/output circuit 1100 is transmitting data and the second input/output circuit 1200 is receiving data. The control circuit 1130 in the output buffer 1120 generates a signal that is the result of inverting the data from the data source 1150 by an inverter INV and supplies this signal to the CMOS inverter (composed of MP101 and MN101).
Further, the control circuit 1140 turns off the switch SW1 between the terminating resistor R101 and high-potential power supply VDDQ and the switch SW2 between the terminating resistor R102 and low-potential power supply GND, whereby the resistors R101 and R102 are disconnected from the line that is connected to the pin DQ.
In the second input/output circuit 1200 at receive time, on the other hand, the control circuit 1230 receives a control signal (output disable) and sets the gate of the P-channel MOS transistor MP201 to the high-potential power supply voltage VDDQ and the gate of the N-channel MOS transistor MN201 to the low-potential power supply voltage GND, thereby placing both of these transistors in the OFF state. Further, the input buffer 1210 is set in the ON state. Further, the control circuit 1240 turns on the switch SW3 between the resistor R201 and high-potential power supply VDDQ and the switch SW4 between the resistor R202 and low-potential power supply GND, whereby the resistors R201 and R202 are connected to the line that is connected to the pin DQ. Thus the circuit operates as a terminating circuit.
The specification of Japanese Patent Kokai Publication JP-A-9-83411 discloses the structure of a semiconductor integrated circuit so adapted that a transmission line will not be terminated when an output drive circuit is driving and controlling a potential on an input/output pad. This circuit serves as an active terminating circuit, which occupies a small area, for avoiding contention with a terminating operation at the time of data output and performing a terminating operation at the time of data reception. This arrangement is such that the terminating circuit that terminates a transmission line connected to an input/output pad is provided separate from an input/output circuit comprising an input buffer circuit and an output buffer circuit. This arrangement is substantially equivalent to the conventional interface circuit described above with reference to FIG. 9.
Further, the specification of U.S. Pat. No. 5,602,494 discloses the structure of a bi-directional programmable I/O cell that functions in a data transmission mode and active termination mode.